(a) Field of the Invention
The present invention relates to a semiconductor device having a stacked capacitor and, more particularly, to a technique for reducing dimensions of a semiconductor device having a stacked capacitor while assuring a higher capacitance of the stacked capacitor. The present to invention also relates to a method for manufacturing such a semiconductor device.
(b) Description of the Related Art
Semiconductor devices have been developed to reduce the dimensions and increase the scale and functions thereof. In particular, DRAM devices now on the market have a capacity of giga-bit order with a reduced design rule of 110 nm (F110-rule), and next-generation DRAM devices will have such an order of capacity with a further reduced design rule of 90 nm (F90-rule). In such a development of finer design rule, a stacked capacitor used in each memory cell of the DRAM device also has reduced dimensions, which makes it difficult for the stacked capacitor to have a required capacitance.
In a F110-rule DRAM device, a technique for achieving a higher capacitance and a finer design rule in the stacked capacitor generally uses a HSG (Hemispherical Silicon Grain), wherein the top and bottom electrodes in the capacitor have a larger opposing area therebetween. However, in the F90-rule DRAM device, it is difficult to use the HSG structure due to the finer design rule, wherein the polysilicon bottom electrode is not allowed to have the HSG structure because of the difficulty in formation of the hemispherical grains on the surface thereof.
Another technique for achieving a higher capacitance and a finer design rule in the stacked capacitor is such that a capacitor insulation film is made of tantalum oxide having a higher dielectric constant compared to the silicon oxide generally used heretofore. However, the tantalum oxide has a problem of occurring of silicon oxynitride film having a lower dielectric constant, after the silicon electrode reacts with an adjacent tantalum oxide film in a heat treatment conducted for reducing a leakage current in the capacitor.
The silicon oxynitride is formed in an oxidizing atmosphere of the heat treatment, after formation of silicon nitride due to reaction between the silicon electrode and the tantalum oxide film. The resultant silicon oxynitride has a thickness of around 3.5 to 4.0 nm, for example, and reduces the capacitance of the stacked capacitor due to the lower dielectric constant thereof. The technique using the tantalum nitride film in the stacked capacitor is described in JP-A-2000-12796, for example.